For a long time, in order to achieve a higher chip density, a faster operating speed and a lower power consumption, a feature size of a metal-oxide-semiconductor field effect transistor (MOSFET) is continuously scaled down according to Moore's law, and currently has reached a nanometer level. However, a serious challenge is an emergence of a short-channel effect, such as a subthreshold voltage roll-off (Vt roll-off), a drain-induced barrier lowering (DIBL) and a source-drain punch through, thus significantly increasing an off-state leakage current. Therefore, a performance of the MOSFET may be deteriorated.
At present, in order to reduce the negative influence of short-channel effect, a variety of improvements have been proposed, especially the tunneling field effect transistor (TFET). When the MOSFET device is in a subthreshold state, the device is of weak inversion type, and the main conductive mechanism is thermoelectron emission. Therefore, the MOSFET's subthreshold slope at room temperature is limited to 60 mV/dec. Compared with a conventional MOSFET, on the one hand, because an active region of the TFET device is substantially a tunneling junction, the TFET has a weaker short-channel effect or even has no short-channel effect; on the other hand, because a main current mechanism of the TFET is band-to-band tunneling and an exponential relationship is formed between a drain current and an applied gate-source voltage in a subthreshold region and a saturation region, the TEFT has a lower subthreshold slope, and a drain current is almost independent of a temperature.
A method for forming a TFET is compatible with a method for a conventional complementary metal-oxide-semiconductor field effect transistor (CMOSFET). The structure of a TFET device is based on a metal-oxide-semiconductor gated P-I-N diode. FIG. 1 is a cross-sectional view of a conventional TFET with an n-type channel. Particularly, the conventional TFET comprises a p-type doped source region 1000′, an n-type doped drain region 2000′, a channel region 3000′ between the p-type doped source region 1000′ and the n-type doped drain region 2000′, and a gate stack 4000′ which comprises a gate dielectric layer formed on the channel region 3000′ and a gate electrode formed on the gate dielectric layer.
When the TFET is turned off, that is, no gate voltage is applied, a junction formed between the source region 1000′ and the drain region 2000′ is a reverse biased diode, and a potential barrier created by the reverse biased diode is greater than that created by a conventional complementary MOSFET, thus greatly reducing a subthreshold leakage current and a direct tunneling current of the TFET even if a channel length is very short. When a voltage is applied to a gate in the TFET, under an action of a field effect, an electron channel may be formed in the channel region 3000′. Once an electron concentration in the channel region 3000′ is degenerated, a tunneling junction will be formed between the source region 1000′ and the channel region 3000′, and a tunneling current generated by carrier tunneling will pass through the tunneling junction. From the perspective of an energy band, with the tunneling field effect transistor based on a gated P-I-N diode, a tunnel length of a P-N junction formed between the source region 1000′ and the channel region 3000′ is adjusted by controlling the voltage of the gate.
The shortcomings of the conventional TFET in the prior art are that the performance of the conventional TFET is not satisfactory yet, in particular, the source-drain capacitance may result in an increase in a delay of digital circuits.